Integrated circuit (IC) devices typically include numerous transistors that are fabricated on, for example, silicon wafers. To increase production yields and lower total IC device costs, semiconductor manufacturers are continually striving to reduce the size of the transistors in IC devices. However, for a given power supply voltage, the electric field strength, e.g., the change in voltage per unit length, that these transistors are exposed to increases as the size of the transistors is reduced. As IC device geometries shrink to the deep sub-micron level (i.e. less than 0.5 um), the electric fields generated by the 5V supply voltages historically used to power IC devices can degrade or even destroy the transistors in those IC devices. For example, the performance of a sub-micron MOS transistor having an effective channel length of 0.35 um is impaired under a 5V supply voltage due to injection of hot electrons into the gate of the MOS transistor. In addition, the electric field generated by a 5V supply voltage across a sub-micron MOS transistor can also cause total failure due to gate oxide breakdown. Therefore, a reduced power supply voltage must be available to reap the cost and efficiency benefits of deep sub-micron transistors while maintaining overall IC performance and reliability. The recent trend towards the use of 3.3V supply voltages is indicative of this need, and further reductions in supply voltages will become necessary as IC device geometries continue to shrink.
At the same time, a 3.3V external supply voltage will not necessarily be available to power deep sub-micron IC devices. While memory and microprocessor boards can often be custom designed to provide 3.3V to those IC devices, other types of IC devices may not have that option available. For example, Programmable Logic Devices (PLD's) are a type of IC device comprising user-configurable logic elements and interconnect resources that are programmable to implement user-defined logic operations (that is, a user's circuit design). PLD's have begun to incorporate 0.35 um transistors that require the 3.3V power supply voltage. However, because of their configurable purpose, PLD's will often be used in systems that operate under 5V power supply voltages due to other IC devices in the system that require 5V, such as TTL or ECL devices. Therefore, many IC devices include a voltage down converter (VDC) to reduce an external power supply voltage to the level required by the transistors in those IC devices.
FIG. 1a shows a conventional VDC 100 used in the EPF10K50V PLD from ALTERA Corporation in San Jose, Calif. VDC 100 comprises NMOS transistors 101, 102, and 103, and an adjustment circuit 105. NMOS transistor 103 is coupled between an external power supply voltage terminal and an output terminal 104. Adjustment circuit 105 is coupled between output terminal 104 and the gate terminal of NMOS transistor 103. NMOS transistors 101 and 102 are both drain-gate coupled and are serially connected between the external power supply voltage terminal and the gate terminal of NMOS transistor 103. As a result, an external supply voltage Vccext at the external power supply voltage terminal is reduced by the threshold voltage drops across NMOS transistors 101 and 102, thereby applying a voltage Vg to the gate terminal of transistor 103. Voltage Vg is given by the equation: EQU Vg=Vccext-Vtn(101)-Vtn(102) [1]
where Vtn(101) and Vtn(102) are the threshold voltage drops across NMOS transistors 101 and 102, respectively. Voltage Vg brings NMOS transistor 103 into conduction, thereby providing a reference voltage Vccint at output terminal 104. Reference voltage Vccint is given by the equation: EQU Vccint=Vg-Vtn(103) [2]
where Vtn(103) is the threshold voltage drop across NMOS transistor 103. Therefore, reference voltage Vccint is effectively "programmed" by NMOS transistors 101, 102, and 103. If the three NMOS transistors are matched, combining equations [1] and [2] yields: EQU Vccint=Vccext-3Vtn [3]
where Vtn is the threshold voltage drop across each of NMOS transistors 101, 102, and 103. Because voltage vg is less than external supply voltage Vccext, NMOS transistor 103 cannot provide a voltage Vccint greater than voltage Vg at output terminal 104. Therefore, NMOS transistors 101 and 102 effectively "program" reference voltage Vccint. For example, a typical value for the threshold voltage drop of an NMOS transistor is 0.5V. In that case, the reference voltage Vccint provided by VDC 100 for an external supply voltage Vccext of 5.0V would be 3.5V (i.e., 5.0V-3*(0.5V)=3.5 V), which would be suitable for driving 3.3V IC devices. Adjustment circuit 105 helps to maintain output stability under load variations. If the load current required from output terminal 104 increases, adjustment circuit 105 forces voltage Vg higher to drive more current through NMOS transistor 103. On the other hand, if voltage Vccint rises excessively, adjustment circuit 105 decreases voltage Vg to compensate. However, although VDC 100 is a simple circuit for providing a reduced reference voltage, it is unacceptable for situations requiring a precise, stable reference voltage. First, any variations in the value of external supply voltage Vccext directly affect the value of reference voltage Vccint. In addition, the threshold voltage drop Vtn across transistors 101 and 102 varies with process, making a specific reference voltage Vccint difficult to achieve. Finally, the threshold voltage drop Vtn also varies with temperature, leading to fluctuations in reference voltage Vccint during normal operation of VDC 100.
FIG. 1b shows a VDC 110, as described by Ishibashi et al. in "A Voltage Down Converter with Submicroampere Standby Current for Low-Power Static RAM's" (IEEE Journal of Solid-State Circuits, Vol. 27, No. 6, June 1992.). VDC 110 provides a stable reference voltage of 4.5V to optimize power dissipation, reliability, and operation speed in a static random access memory (SRAM). VDC 110 comprises a depletion-mode NMOS transistor 112, matched PMOS transistors 131-133, matched NMOS transistors 141-145, matched NMOS transistors 151-153, and matched depletion-mode NMOS transistors 161-163. Depletion-mode NMOS transistor 112, PMOS transistor 131, and NMOS transistor 141 are serially coupled between an external voltage supply terminal and ground. PMOS transistor 132 and NMOS transistor 142 are serially coupled between the external voltage supply terminal and ground. PMOS transistor 133 and depletion-mode transistors 151-153 are serially coupled between the external voltage supply terminal and ground. Finally, depletion-mode NMOS transistors 161-163 are serially coupled with NMOS transistors 143-145, respectively, between the external voltage supply terminal and ground.
When a voltage Vccext is applied to the external Vcc supply terminal, gate-source coupled depletion-mode NMOS transistor 112 is forced to operate in its linear region and generates a small programming current Iprog. Because depletion-mode NMOS transistor 112 is operating in its linear region, programming current Iprog is relatively independent of supply voltage and temperature variations. Meanwhile, since the gate and drain terminals of PMOS transistor 132 are coupled to the gate terminal of PMOS transistor 131, PMOS transistor 132 is biased into conduction and attempts to mirror the current flowing through PMOS transistor 131. Similarly, because the gate and drain terminals of NMOS transistor 141 are coupled to the gate terminal of NMOS transistor 142, NMOS transistor 141 is biased into conduction and attempts to mirror the current flowing through NMOS transistor 142. As a result, programming current Iprog flows through PMOS transistor 131 and NMOS transistor 141, and a reference current Iref equal to programming current Iprog flows through PMOS transistor 132 and NMOS transistor 142. A gate voltage Vgp at the commonly connected gate terminals of PMOS transistors 131 and 132 is applied to the gate terminal of PMOS transistor 133. Voltage Vgp forces PMOS transistor 133 to conduct a current Ia, which is equal to programming current Iprog. Gate-drain coupled NMOS transistors 151-153 are sized to produce a threshold voltage drop Vtn when current Ia is equal to current Iprog, so the voltage at node A is 3*Vtn. At the same time, a gate voltage Vgn at the commonly connected gate terminals of NMOS transistors 141 and 142 is applied to the gate terminals of NMOS transistors 143-145. Gate voltage Vgn forces NMOS transistors 143, 144, and 145 to conduct currents Ib, Ic, and Id, respectively, where currents Ib-Id are all equal to programming current Iprog. Depletion-mode NMOS transistors 161-163 are sized to conduct a current equal to current Iprog when biased by a gate-drain voltage V'tn. Therefore, the voltage at node B is 3*Vtn-V'tn. Similarly, the voltage at node C is 3Vtn-2V'tn, and the voltage at node D is 3Vtn-3V'tn. Therefore, the output voltage Vccint of VDC 110 is given by the equation: EQU Vccint=3.DELTA.Vtn [4]
where .DELTA.Vtn is equal to the threshold voltage difference between enhancement-mode NMOS transistors 151-153 and depletion-mode NMOS transistors 161-163 (i.e., Vtn-V'tn). In this manner, VDC 110 provides a reduced supply voltage. The characteristics of NMOS transistors 151-153 and depletion-mode NMOS transistors 161-163 determine the value of output voltage Vccint. For example, when the As.sup.+ channel dopant concentration in depletion-mode NMOS transistors 161-163 is 3.times.10.sup.12 cm.sup.-2, a programming current Iprog of 30 nA produces a threshold voltage difference .DELTA.Vtn of 1.45 V. Output voltage Vccint then becomes 4.35 V, the desired SRAM supply voltage. Because of the stability of programming current Iprog provided by depletion-mode NMOS transistor 112, VDC 110 produces a more constant output voltage than does VDC 100 from Altera Corporation. However, because VDC 110 is dependant on transistor threshold voltage drops to set output voltage Vccint, manufacturing process variations can still make specific values of output voltage Vccint difficult to achieve. In addition, output voltages Vccint that are not integral multiples of threshold voltage difference .DELTA. Vtn cannot be achieved.
Accordingly, it is desirable to provide a VDC that provides a stable reference output voltage that is immune to temperature and manufacturing process variations, and can be set to a desired output voltage value.